Hello Soby/Joanna,
We would like to upstream support for a new Tegra platform along with some other changes. The last time I checked, there were more than 400 changes waiting to be upstreamed.
Can someone help me with the best/fastest approach to start upstreaming? Previously, we would upstream changes in big chunks (as branches) but I don't know if that approach still works.
Thanks.
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Hi Soby,
> Hmm, if we merge a non-trivial patch and ensure the build works, then we
> do not know whether it runs correctly, whether there are any runtime
> effects that would affect stability/robustness of the platform that even
> might have security implications. Hence, in my view, it is better to
> have a broken build for the platform, rather than have runtime problems.
>
> The project could form a policy that if a platform remains broken for
> more than 2 releases (1 year by current release intervals), then it will
> get removed from the tree after giving enough notifications.
Thanks, yes, I think it would be good to have a clear policy on this,
whatever it is.
I would still like to make a case for keeping these platforms in the
tree on a best-effort basis. You're right that there's a chance for
untested patches to cause all sorts of runtime errors, but I think
that may still be better than a platform that doesn't build at all. A
platform that doesn't build doesn't benefit anyone. A platform that
may have errors still has a chance of working, and even if it doesn't
it gives a third-party contributor or hobby developer who wants to
start using it a chance to fix it up again. This is something we
occasionally see happening with some of our older, less maintained
platforms in coreboot. But if it doesn't even build, the chance of
someone coming along to fix it seem very slim, because then more and
more build issues will keep piling up over time. (In fact, I doubt
there's even any point in keeping broken stuff in the tree for another
year as you proposed... likely all that would do is confuse people who
are trying to refactor project-wide APIs. Code that's never
build-tested just bit rots very quickly. I think at that point you
might as well remove it from the repo immediately.)
It's true that there may also be security issues (which is more
serious), but I'm skeptical that this really makes a lot of
difference. After all, this may happen even while the platform is
still actively maintained. Just testing whether it boots doesn't make
sure you have no security issues anyway. Maybe a way to make this more
visible instead could be to introduce a new
ALLOW_UNMAINTAINED_PLATFORM=1 make variable that the user has to
explicitly set to build a platform without active maintainer? That
could serve as a warning that the code may not be safe to use for
critical applications anymore while still giving developers access to
something if they're willing to deal with possible issues.
Anyway, whatever the policy may be, a more defined process would help.
I think the initial messaging around the console deprecation plan was
fine, but it would have been good to have another explicit
announcement when the CI actually gets turned off for a platform.
Hi Julius,
On 8/27/19 9:55 PM, Julius Werner via TF-A wrote:
> Could either of you please help get the Tegra fix in
> https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1192
> landed (and subsequently CI for Tegra re-enabled)? It has been
> reviewed and approved for two weeks but nobody is merging it. This is
> blocking more and more work across all coreboot-based platforms so I
> would appreciate if we could get it resolved quickly.
Apologies for the delay. As you may have seen, the patch has now been
merged, and we've also re-enabled the Tegra builds in the CI.
Regards,
Sandrine
Hi Soby, Joanna,
Could either of you please help get the Tegra fix in
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1192
landed (and subsequently CI for Tegra re-enabled)? It has been
reviewed and approved for two weeks but nobody is merging it. This is
blocking more and more work across all coreboot-based platforms so I
would appreciate if we could get it resolved quickly.
Thanks,
Julius
Hi Julius
> -----Original Message-----
> From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Julius
> Werner via TF-A
> Sent: 20 August 2019 02:15
>
> Hi Soby et. al.,
>
> I'd like to implement a small new feature and ask some guidance for how to go
> about it: Chrome OS has the ability to automatically collect crash reports
> from runtime crashes in Trusted Firmware, and we would like to set up
> automated tests to ensure this feature stays working.
> In order to do this we need a way for the non-secure OS to intentionally
> trigger a panic in EL3. The obvious solution would be to implement a new SMC
> for that. (It's common for operating systems to have similar facilities, e.g.
> Linux can force a kernel panic by writing 'c' into /proc/sysrq-trigger.)
>
OK I can see the use of that, although I'd be a bit concerned about such a thing being available as a general service in case it gets used as an attack vector. For example, a test program could aggressively use this service to try to get the firmware to leak secure world information or something about its behaviour.
> My main question is: where should I get an SMC function ID for this?
> This is not a silicon or OEM specific feature, so the SiP Service Calls and
> OEM Service Calls ID ranges seem inappropriate (or do you think it would make
> sense to treat Google or Chrome OS as the "OEM"
> here, even though that's not quite accurate?).
I guess in theory you could mandate that all Chrome OS SiPs provide a specific function ID in their own specific SiP service, but I don't think that's the right solution here...
> There are ranges for Trusted
> Applications and the Trusted OS but unfortunately none for the normal world
> OS.
I don't think the TOS range is right either.
> Is this something that would make sense to allocate under Standard
> Service Calls? Could you just find an ID for me to use there or does
> everything in that range need a big specification document written by Arm?
>
For sure everything in the standard or architectural ranges require specification by Arm, although this does not necessarily need to be big.
However, I think there might already be support for what you need. PSCI is part of the standard service and the function SYSTEM_RESET2 allows for both architectural and vendor-specific resets. The latter allows for vendor-specific semantics, which could include crashing the firmware as you suggest.
Chrome OS could specify what such a vendor-specific reset looks like and each Chromebook's platform PSCI hooks could be implemented accordingly.
Alternatively, this could potentially be defined as an additional architectural reset. This would enable a generic implementation but would require approval/definition by Arm's Architecture team. Like me they might have concerns about this being defined at a generic architectural level.
Regards
Dan.
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Hi Soby et. al.,
I'd like to implement a small new feature and ask some guidance for
how to go about it: Chrome OS has the ability to automatically collect
crash reports from runtime crashes in Trusted Firmware, and we would
like to set up automated tests to ensure this feature stays working.
In order to do this we need a way for the non-secure OS to
intentionally trigger a panic in EL3. The obvious solution would be to
implement a new SMC for that. (It's common for operating systems to
have similar facilities, e.g. Linux can force a kernel panic by
writing 'c' into /proc/sysrq-trigger.)
My main question is: where should I get an SMC function ID for this?
This is not a silicon or OEM specific feature, so the SiP Service
Calls and OEM Service Calls ID ranges seem inappropriate (or do you
think it would make sense to treat Google or Chrome OS as the "OEM"
here, even though that's not quite accurate?). There are ranges for
Trusted Applications and the Trusted OS but unfortunately none for the
normal world OS. Is this something that would make sense to allocate
under Standard Service Calls? Could you just find an ID for me to use
there or does everything in that range need a big specification
document written by Arm?
Thanks,
Julius
Hi Marek
The patch is available at
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1789
Regards.
Alexei
________________________________
From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Joanna Farley via TF-A <tf-a(a)lists.trustedfirmware.org>
Sent: 19 August 2019 11:41
To: Marek <marek.bykowski(a)gmail.com>
Cc: tf-a(a)lists.trustedfirmware.org <tf-a(a)lists.trustedfirmware.org>
Subject: Re: [TF-A] Advisory TFV 5 to CVE-2017-15031 only saves/stores the PMCR_EL0 across world switching
Hi Marek,
Changes are in review so hopefully soon.
Joanna
On 19/08/2019, 10:56, "TF-A on behalf of Marek via TF-A" <tf-a-bounces(a)lists.trustedfirmware.org on behalf of tf-a(a)lists.trustedfirmware.org> wrote:
Hi Dan,
Are there any time estimates when the fix should be in?
Thanks,
Marek
On Sat, 10 Aug 2019 at 22:46, Marek via TF-A
<tf-a(a)lists.trustedfirmware.org> wrote:
>
> Thank you Dan for checking this out. Looking forward into the fix.
>
> Marek
>
> On Thu, 8 Aug 2019 at 17:52, Dan Handley via TF-A
> <tf-a(a)lists.trustedfirmware.org> wrote:
> >
> > Hi Marek
> >
> > Thanks for pointing this out. Typically we expect any timing sensitive secure operations to be implemented at Secure-EL1 or lower, which the current code does protect. However, you are correct that all secure world code including EL3 should not expose timing information. A fix is in progress to address this.
> >
> > Regards
> >
> > Dan.
> >
> > > -----Original Message-----
> > > From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Marek
> > > Bykowski via TF-A
> > > Sent: 03 August 2019 07:37
> > > To: tf-a(a)lists.trustedfirmware.org; David Cunado <David.Cunado(a)arm.com>
> > > Subject: [TF-A] Advisory TFV 5 to CVE-2017-15031 only saves/stores the
> > > PMCR_EL0 across world switching
> > >
> > > Hi David/ATF Support,
> > >
> > > An excerpt from the commit message to CVE-2017-15031 is "Additionally,
> > > PMCR_EL0 is added to the list of registers that are saved and restored during
> > > a world switch."
> > >
> > > My question is why it is only being saved/restored across the world switch
> > > and not during a "normal" SMC call? When I do modify the
> > > PMCR_EL0 in EL2 or NonSecure-EL1 and run the smc call the PMCCNTR counter
> > > counts during the smc call and does expose secure world timing information to
> > > NonSecure in that matter.
> > >
> > > Thanks,
> > > Marek
> > > --
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> > > https://lists.trustedfirmware.org/mailman/listinfo/tf-a
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>
>
>
> --
> Slán,
> Marek
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Marek
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