It is observed that several unused functions are present in Trusted Firmware-A code, is it possible to mask those unused functions or leave them as it is to fix MISRA-C Violations? If these functions are not appearing in symbol table, then no need to take actions on violations reported in these functions? Please suggest.
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Hi All,
SCR_EL3.EA define whether to route External Abort and SError Interrupt to EL3 or EL2/1. ATF have a compile time flag to HANDLE_EA_EL3_FIRST_NS to program SCR_EL3.EA.
Below text from ATF documentation.
- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError
Interrupts, resulting from errors in NS world, will be always trapped in
EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions
will be trapped in the current exception level (or in EL1 if the current
exception level is EL0).
Have question related to forwarding of these errors when External Abort and SError Interrupt are routed to EL3.
In this case will ATF forward Asynchronous SError Interrupt to Linux via RAS?
Thanks
-Bharat
It is observed that functions like macros like NOTICE, WARN and assert are present in the Trusted Firmware-A code. MISRA-C standard treats these as violations. shall we take these as deviation? please suggest.
TFA Guidelines recommends using logging macros. So can we make deviations or need to change the MACRO into function.
Hello,
It is observed that device tree functions are present under lib/libfdt/... in Trusted Firmware-A code, but this device tree are not present in symbol table and also if we remove this device tree functions in code, board was successfully booting. However, while doing Coverity build to fix MISRA-C violations getting violations from this device tree code.
So, is it possible to leave those violations please suggest? And when it will be enabled, please suggest.
Thanks & Regards
Nithin G
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Hi
I ported TF-A and OPTEE on multi-core SoC, and I checked that xtest passed
on CPU0 without failure. However, I'm failing in secondary CPU boot, and
I'd like to get some help.
I'm using ARMv8, and I'm using spintable as CPU enable method (not using
PSCI FW). TF-A is in EL3.
What I did ...
1. I released secondary CPU reset from bl31_early_platform_setup2() during
primary CPU cold booting
- set secondary CPU's RVBAR to bl31_entrypoint
- release secondary CPU reset
2. I implemeneted plat_secondary_cold_boot_setup(), which is spining until
linux kernel updates cpu-release-addr. Once linux kernel updates
cpu-release-addr, then it changes EL to EL1 and jumps to
secondary_startup() in linux
3. But secondary core goes to panic. It seems to happen when linux invokes
optee_probe()
Should I initialize some contexts (e.g. optee ..)? If so, where should I
implement the corresponding codes? I'm wondering if I'm missing something,
and I'd like to get some advice
Thanks,
--Bin
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