On the page A2-119 In an Armv8.4 implementation, if FEAT_RAS is implemented, FEAT_RASv1p1 is implemented. FEAT_RASv1p1 is OPTIONAL from Armv8.2.

Reason for no details of SCR in CPU TRMs is becasue it should be read in conjunction with Arm ARM

[1]: https://developer.arm.com/documentation/ddi0487/latest/

From: Nagal, Amit via TF-A <tf-a@lists.trustedfirmware.org>
Sent: 08 May 2024 10:15
To: tf-a@lists.trustedfirmware.org <tf-a@lists.trustedfirmware.org>
Subject: [TF-A] FAULT_INJECTION_SUPPORT - FIEN bit

Hi,

Referring https://github.com/ARM-software/arm-trusted-firmware/blob/master/docs/getting_started/build-options.rst
it says : ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault injection from lower Els.

Referring https://github.com/ARM-software/arm-trusted-firmware/blob/master/lib/el3_runtime/aarch64/context_mgmt.c#L396:L398
FAULT_INJECTION_SUPPORT enables FIEN bit.
#if FAULT_INJECTION_SUPPORT
        /* Enable fault injection from lower ELs */
        scr_el3 |= SCR_FIEN_BIT;
#endif

Question :
1.
Do we have any relevant documentation from arm which specifies FIEN bit can be enabled from armv8.4 ?

2.
In cortex a-53 technical reference manual, SCR_EL3 does not have FIEN bit , bit 21 is marked reserved .
In cortex a-78 technical reference manual ,  manual does not have details for SCR_EL3 .
I want to know whether on Armv8.2-a based cores like cortex a-78 , is the FIEN bit field marked reserved in SCR_EL3 register or is available functionality wise as in armv8.4 ?
Please help with above query.

Regards
Amit

--
TF-A mailing list -- tf-a@lists.trustedfirmware.org
To unsubscribe send an email to tf-a-leave@lists.trustedfirmware.org