Hi All

We are trying to implement errata which is applicable for below CPUs:

Cortex-A53: 1530924

Cortex-A76: 1165522
Cortex-A72: 1319367
Cortex-A57: 1319537
Cortex-A55: 1530923

Errata Description:

A speculative Address Translation (AT) instruction translates using registers that are associated with an out-of-context translation regime and caches the resulting translation in the TLB. A subsequent translation request that is generated when the out-of-context translation regime is current uses the previous cached TLB entry producing an incorrect virtual to physical mapping.

Probable solution is to implement below fix in context.S file:

During ELx (1 or 2) context save:

· Operate TCR_ELx(1/2) to disable page table walk by operating EPD bits

o This will avoid any page table walk for S-EL1 or S-EL2. This will help in avoiding caching of translations in TLB

for S-EL1/S-EL2 in EL3.

· Save all system registers (which is already available) except TCR

· Clear EPD bits of TCR and then save. (Just to enable PTW during restore context).

During ELx (1 or 2) context restore:

Operate TCR_ELx(1/2) to disable page table walk by operating EPD bits
Restore all system registers (which are saved during context save) except TCR register.
Restore TCR_ELx(1/2) register (which enable back PTW).

With above we ensured that there will be no page table walk for S-EL1 and S-EL2 in EL3.

is this proper other way to fix this problem? Need some suggestion/use cases where and all we need this workaround in TF-A code.

Thanks

Manish Badarkhe