2026

2025

2024

2023

2022

2021

2020

List overview
Download

TF-M-ci-notifications

tf-m-ci-notifications@lists.trustedfirmware.org

7221 discussions

Start a nNew thread

LAVA notification for Test Job 2803866 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF_187662_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2803866 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2803866 Infrastructure error: Flash failure indicated by presence of FAIL.TXT (Details: The hex file cannot be decoded. Checksum calculation failure occurred.) Device details: Hostname: musca-b-03 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF_187662_musca-b Submitted: 2025-09-21 23:53:06 (+0000 UTC) Started: 2025-09-22 02:04:32 (+0000 UTC) Finished: 2025-09-22 02:09:33 (+0000 UTC) Duration: 0:05:01 -- LAVA Linaro Automated Validation Architecture

6 months, 1 week

1
0
0 0

LAVA notification for Test Job 2803801 MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_187547_musca-b

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2803801 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2803801 Test error: lava-test-monitor timed out after 1200 seconds Device details: Hostname: musca-b-03 Type: musca-b Owner: None Worker: w1 Job details: Priority: Medium Description: MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_187547_musca-b Submitted: 2025-09-21 23:49:57 (+0000 UTC) Started: 2025-09-22 00:59:02 (+0000 UTC) Finished: 2025-09-22 01:25:10 (+0000 UTC) Duration: 0:26:08 -- LAVA Linaro Automated Validation Architecture

6 months, 1 week

1
0
0 0

Job tf-m-nightly test 125 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/125/ Failed Jobs: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tf.validation.linaro.org/scheduler/job/2799504 For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/125/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 months, 2 weeks

1
0
0 0

Job tf-m-nightly build 120 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/120/ Failed Jobs: MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170809/ MUSCA_B1_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170537/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/170567/ MUSCA_B1_ARMCLANG_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170650/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/170665/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/170734/ MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170760/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170796/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/170815/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC3XX_RUNTIME_ENABLED https://ci.trustedfirmware.org/job/tf-m-build-config/170587/ MUSCA_B1_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170595/ MUSCA_B1_ARMCLANG_2_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170609/ MUSCA_B1_ARMCLANG_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170647/ MUSCA_B1_ARMCLANG_3_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170733/ MUSCA_B1_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170810/ MUSCA_B1_ARMCLANG_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170887/ MUSCA_B1_ARMCLANG_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170900/ MUSCA_B1_ARMCLANG_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170949/ MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170966/ MUSCA_B1_ARMCLANG_2_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/171008/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/171015/ MUSCA_B1_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/171025/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/171036/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/171040/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/171042/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/171048/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/171062/ MUSCA_B1_ARMCLANG_2_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170987/ MUSCA_B1_ARMCLANG_2_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/171030/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/170548/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/170552/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/170566/ MUSCA_B1_ARMCLANG_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170573/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170624/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170631/ MUSCA_B1_ARMCLANG_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170649/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/170655/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170668/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170679/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/170718/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170723/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170726/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170742/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170748/ MUSCA_B1_ARMCLANG_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170767/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/170785/ MUSCA_B1_ARMCLANG_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170816/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/170818/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170826/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/170830/ MUSCA_B1_ARMCLANG_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170832/ MUSCA_B1_ARMCLANG_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170843/ MUSCA_B1_ARMCLANG_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170856/ MUSCA_B1_ARMCLANG_3_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170885/ MUSCA_B1_ARMCLANG_1_Debug_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/170890/ MUSCA_B1_ARMCLANG_3_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170898/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/170902/ MUSCA_B1_ARMCLANG_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170920/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/170923/ MUSCA_B1_ARMCLANG_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170947/ MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/170951/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/170954/ MUSCA_B1_ARMCLANG_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170956/ MUSCA_B1_ARMCLANG_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170967/ MUSCA_B1_ARMCLANG_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/170970/ MUSCA_B1_ARMCLANG_3_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/170986/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/171072/ For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/120/artifact/build_results.… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 months, 3 weeks

1
3
0 0

Job tf-m-nightly test 114 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/114/ Failed Jobs: AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQcYaKauqUU6w… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQcfG9jA2mYnq… AN521_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQcoSgsBvPY7G… AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPON_LZOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQcunXbLGA9WC… AN521_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQd0noRvm3f6R… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQd9EqBSrkwCD… AN521_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQdIEat6ZlND6… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQdMl64wpTRWf… AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPON https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQdadMsW62JSn… AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQdczCM8hw2ln… AN521_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQdmtFq3kOE0P… AN521_GCC_3_RegBL2_RegS_RegNS_Debug_BL2_LARGE_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQdnA7ERc6Upc… AN521_GCC_3_RegBL2_RegS_RegNS_Release_BL2_LARGE_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQduTEGGmUZDl… AN521_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON_LZOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQe232HjXSeTH… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQeB8GqkJ9hmA… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQeGw5la9cYM7… AN521_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2_LARGE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQeRIvJEnDzqu… AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_FPOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQeah9ndm9K51… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_SMALL_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQeeouX6Hqlby… AN521_GCC_3_RegBL2_RegS_RegNS_Debug_BL2_LARGE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQepEIYoP3Hz8… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQekWrxweOg1I… AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQeuwGE3LjeK1… AN521_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQf2jV8N4dbpU… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQf77pHADMnj5… AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPON https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQfM4EqEdZjx6… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_SMALL_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQfSlhLoThGaT… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MMIO https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQfUSGRh5eo92… AN521_GCC_2_RegBL2_RegS_RegNS_Release_BL2_FPON https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQfffhlAG90Sr… AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQfqxdlkUtZZ8… AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQfuh7HEHHAOP… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQg28GkhitlSZ… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQgE8DNqyNjZu… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQgIsZIkym6nS… AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQgQA0LRZYbFJ… AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQgRB0fUlWN70… AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQgXpoTRYWj1l… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQgh6Xa8Fvwml… AN521_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQgomgm48hvk4… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQgxs8aYXKeyD… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQh1BCrlKWJBe… AN521_GCC_2_RegBL2_RegS_RegNS_Release_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQhDQxi7A1MER… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2_LARGE_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQhITv7Lvk3iu… AN521_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQhQk7pEGxKNC… AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MMIO https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQhS9GomngqDK… AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_SMALL_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQhZYxne40V6l… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQheg0EKvDf9m… AN521_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_SMALL_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQhqRJxy95KiL… AN521_GCC_3_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQhsnkGf2Zrev… AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPON https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQi7PaZMjcTbw… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_SMALL_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQi85nXLAMmHj… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2_LARGE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQiMo0pzVRXsX… AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQiS5NTSuoMM8… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQiOaJqzPwNEy… AN521_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2_LARGE_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQiVtye5kSFIP… AN521_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQiiVWNlbyCTE… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQiqS7t2a4imv… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MMIO https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQixZcSnhxqn3… AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQiygzGg4VCpF… AN521_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQj6xC78eRmRQ… AN521_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQjA4jMlwB6cR… AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2_MMIO https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQjLuX9fEvREH… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2_LARGE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQjOUCcI9Kdbk… AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2_FPON_LZOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQjamEsl3tWU6… AN521_GCC_1_RegBL2_RegS_RegNS_Release_BL2_SMALL_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQjilkVW7fNoq… AN521_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MMIO https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQjgMPimK5sBI… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2_LARGE_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQjp7kKIox7FI… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQjuGrL2PjoTY… AN521_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQk7tvFkBdZY1… AN521_GCC_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQkD023pa85MG… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Debug_BL2_LARGE_PSOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQkJOfHoyta9m… AN521_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQkV6FZkNuVj3… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQkRP3FEXDzDY… AN521_ARMCLANG_3_RegBL2_RegS_RegNS_Debug_BL2_LARGE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQkZLoXjA5hxh… AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_FPON_LZOFF https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQkkIdxQbrJ5z… AN521_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_NSCE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQklKlTPhrRLr… AN521_GCC_3_RegBL2_RegS_RegNS_Release_BL2_LARGE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQktqW483NBpQ… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_MMIO https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQl6zKuanYFDA… AN521_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32DQl2XbBpopkaK… For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/114/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

6 months, 3 weeks

1
4
0 0

Job tf-m-nightly test 112 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/112/ Failed Jobs: RSE_TC4_GCC_3_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/327mJni6ohaRG1v… For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/112/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

7 months

1
0
0 0

Job tf-m-nightly test 110 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/110/ Failed Jobs: RSE_TC4_GCC_2_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/32284hy4Hcr4iPE… For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/110/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

7 months

1
0
0 0

Job tf-m-nightly build 106 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/106/ Failed Jobs: AN521_GCC_1_FF_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/151117/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/151286/ RSE_TC4_GCC_1_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/151339/ AN521_GCC_1_Minsizerel_BL2_SMALL_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/151124/ For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/106/artifact/build_results.… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

7 months, 1 week

1
0
0 0

Job tf-m-nightly test 103 fail

by svc_openci_enginfra＠arm.com

Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/103/ Failed Jobs: RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/31iLuL4lwvEp8sT… For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/103/artifact/test_results.c… IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

7 months, 1 week

1
0
0 0

LAVA notification for Test Job 2787288 b_u585i_iot02a_GCC_1_RegS_RegNS_Release_BL2_142460_b-u585i-iot02a

by lava＠tf.validation.linaro.org

Hello, The job with ID # 2787288 is now in state Finished and health Incomplete. Job was submitted by ciadmin_arm. Job details and log file: http://tf.validation.linaro.org/scheduler/job/2787288 Test error: lava-test-monitor timed out after 180 seconds Device details: Hostname: b-u585i-iot02a-02 Type: b-u585i-iot02a Owner: None Worker: w1 Job details: Priority: Medium Description: b_u585i_iot02a_GCC_1_RegS_RegNS_Release_BL2_142460_b-u585i-iot02a Submitted: 2025-08-20 18:20:51 (+0000 UTC) Started: 2025-08-20 18:20:53 (+0000 UTC) Finished: 2025-08-20 18:24:48 (+0000 UTC) Duration: 0:03:55 -- LAVA Linaro Automated Validation Architecture

7 months, 2 weeks

1
0
0 0

Jump to page: