Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/316/
Failed Jobs: RSE_TC4_GCC_3_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3ApKtbOK0QrRpIEg...
For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/316/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/317/
Failed Jobs: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/462125/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/462144/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/462455/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/462406/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/461997/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/462067/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/462734/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/462430/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/462335/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/462058/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/462476/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/462538/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/462079/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/462670/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/462116/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/462520/ MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/462179/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/462516/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/462519/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/462324/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/462499/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/462201/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/462466/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/462394/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/462121/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/462193/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/462123/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/462135/
For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/317/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/318/
Failed Jobs: MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/463334/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/463571/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/463619/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/463809/ MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/464010/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/463978/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/463961/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/463282/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/463685/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/463963/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/463290/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/463745/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/463447/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/463607/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/463442/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/463413/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/463852/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/463955/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/463735/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/463473/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/463467/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/463382/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/463485/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/463423/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/463918/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/463817/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/463452/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/463632/
For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/318/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/319/
Failed Jobs: MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/464724/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/464592/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/464980/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/464587/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/464915/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/464344/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/464345/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/464353/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/464366/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/464477/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/464510/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/464647/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/464823/ MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/464908/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/465010/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465031/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465036/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/464485/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/464541/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/464557/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/464812/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/464814/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/464853/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/464913/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/464978/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/464697/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/464740/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/464774/
For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/319/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/320/
Failed Jobs: MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/465308/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/465300/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465824/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/465330/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/465337/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465327/ MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/465923/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465450/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/465803/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465517/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465566/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/465418/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/465600/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/465947/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/465443/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/465778/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/465521/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/465434/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/465544/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/465451/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/465740/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465813/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/465942/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/465697/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/465522/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/465761/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465941/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/465766/
For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/320/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/321/
Failed Jobs: MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/466709/ AN521_ARMCLANG_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/466837/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/466845/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/466851/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/466979/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/467000/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/467021/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/467027/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/467069/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/467075/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/467132/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/467142/ MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/467207/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/467209/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/467296/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/466930/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/467115/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/467235/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/467247/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/467256/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/467389/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/467402/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/467411/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/467413/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/467428/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/467429/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/467445/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/467446/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/467463/
For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/321/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/322/
Failed Jobs: AN524_GCC_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/469354/
For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/322/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/323/
Failed Jobs: MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/470330/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470352/ RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470093/ MUSCA_B1_ARMCLANG_3_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470126/ MUSCA_B1_GCC_1_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470357/ RSE_TC4_GCC_2_RegBL1_1_Debug_BL2_CM_DM_BL2_ECDSA_SIGNING https://ci.trustedfirmware.org/job/tf-m-build-config/470684/ MUSCA_B1_GCC_3_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470090/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2_TFM_BL1_2_IMAGE_BINDING_ENC_ON_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470109/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470110/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/470130/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470148/ RSE_TC4_GCC_3_RegBL1_1_Debug_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/470171/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470176/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470228/ MUSCA_B1_GCC_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470229/ RSE_TC4_GCC_1_RegBL1_1_Debug_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/470231/ RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2_CM_DM_BL2_ECDSA_SIGNING https://ci.trustedfirmware.org/job/tf-m-build-config/470257/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/470327/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470373/ RSE_TC4_GCC_3_Release_BL2_TFM_BL1_2_IMAGE_BINDING_ENC_ON_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470387/ MUSCA_B1_ARMCLANG_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470407/ MUSCA_B1_ARMCLANG_1_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470457/ RSE_TC4_GCC_3_Release_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470505/ RSE_TC4_GCC_1_Release_BL2_TFM_BL1_2_IMAGE_BINDING_ENC_OFF_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470552/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470562/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470584/ RSE_TC4_GCC_1_RegS_RegNS_Release_BL2_CM_DM_BL2_ECDSA_SIGNING https://ci.trustedfirmware.org/job/tf-m-build-config/470091/ MUSCA_B1_GCC_2_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470092/ RSE_TC4_GCC_1_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470103/ MUSCA_B1_ARMCLANG_1_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470104/ RSE_TC4_GCC_3_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/470111/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/470116/ MUSCA_B1_GCC_3_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470118/ RSE_TC4_GCC_3_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470119/ RSE_TC4_GCC_1_RegBL1_1_Release_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470121/ MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470127/ RSE_TC4_GCC_1_Release_BL2_TFM_BL1_2_IMAGE_BINDING_ENC_ON_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470132/ RSE_TC4_GCC_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470134/ RSE_TC4_GCC_1_RegS_RegNS_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470191/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470205/ MUSCA_B1_GCC_1_ATTEST_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470237/ MUSCA_B1_GCC_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470292/ RSE_TC4_GCC_1_Release_BL2_CM_DM_BL2_ECDSA_SIGNING https://ci.trustedfirmware.org/job/tf-m-build-config/470348/ RSE_TC4_GCC_1_RegBL1_1_Release_BL2_CM_DM_BL2_ECDSA_SIGNING https://ci.trustedfirmware.org/job/tf-m-build-config/470396/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470428/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470436/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/470481/ MUSCA_B1_GCC_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470514/ RSE_TC4_GCC_3_Release_BL2_TFM_BL1_2_IMAGE_BINDING_ENC_OFF_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470519/ RSE_TC4_GCC_3_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/470523/ MUSCA_B1_ARMCLANG_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470544/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470547/ MUSCA_B1_ARMCLANG_2_Debug_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470549/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/470551/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470557/ MUSCA_B1_ARMCLANG_1_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470564/ MUSCA_B1_ARMCLANG_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470565/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/470567/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470569/ MUSCA_B1_ARMCLANG_1_Release_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470571/ RSE_TC4_GCC_1_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/470576/ RSE_TC4_GCC_1_RegBL1_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470578/ MUSCA_B1_GCC_2_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470594/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470604/ MUSCA_B1_ARMCLANG_2_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470605/ RSE_TC4_GCC_1_RegS_RegNS_Debug_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470701/ RSE_TC4_GCC_2_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470747/ RSE_TC4_GCC_2_RegBL1_1_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470789/ RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470791/ RSE_TC4_GCC_2_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470793/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470794/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470798/ RSE_RDV3R1_GCC_3_RegS_Release_BL2_NSOFF_CFG0 https://ci.trustedfirmware.org/job/tf-m-build-config/470801/ MUSCA_B1_ARMCLANG_2_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470803/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470804/ MUSCA_B1_ATFE_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470807/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2_TFM_BL1_2_IMAGE_BINDING_ENC_ON_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470811/ RSE_TC4_GCC_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/470814/ MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Release_BL2_MEDIUM_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470815/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/470816/ RSE_TC4_GCC_2_Debug_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470820/ MUSCA_B1_GCC_2_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470821/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/470824/ MUSCA_B1_GCC_1_Release_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470186/ RSE_TC4_GCC_3_RegS_RegNS_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470194/ MUSCA_B1_ARMCLANG_1_Release_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/470195/ RSE_TC4_GCC_3_RegBL1_1_Debug_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/470198/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/470200/ RSE_TC4_GCC_3_RegBL1_1_Debug_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470201/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2_ATTESTATION_SCHEME_DPE https://ci.trustedfirmware.org/job/tf-m-build-config/470345/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470754/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470758/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2_RSE_RUN_BL1_1_TESTS_IN_PCI https://ci.trustedfirmware.org/job/tf-m-build-config/470773/ RSE_TC4_GCC_3_Debug_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470775/ 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MUSCA_B1_ARMCLANG_2_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470258/ MUSCA_B1_ARMCLANG_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470261/ RSE_RDV3R1_GCC_1_RegS_Release_BL2_NSOFF_CFG0 https://ci.trustedfirmware.org/job/tf-m-build-config/470262/ MUSCA_B1_ARMCLANG_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470265/ MUSCA_B1_ARMCLANG_2_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470266/ RSE_TC4_GCC_3_RegS_RegNS_Release_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470273/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470328/ MUSCA_B1_ARMCLANG_2_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470334/ 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RSE_TC4_GCC_2_RegBL1_1_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470723/ MUSCA_B1_ARMCLANG_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470724/ RSE_TC4_GCC_2_RegS_RegNS_Release_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470802/ MUSCA_B1_ARMCLANG_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470137/ MUSCA_B1_GCC_2_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470145/ RSE_TC4_GCC_3_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470169/ MUSCA_B1_GCC_2_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470278/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470286/ MUSCA_B1_ARMCLANG_3_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470290/ RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470295/ MUSCA_B1_GCC_2_Minsizerel_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470296/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_IPC https://ci.trustedfirmware.org/job/tf-m-build-config/470303/ MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470304/ MUSCA_B1_ARMCLANG_2_Minsizerel_BL2_MEDIUM https://ci.trustedfirmware.org/job/tf-m-build-config/470313/ MUSCA_B1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC3XX_RUNTIME_ENABLED https://ci.trustedfirmware.org/job/tf-m-build-config/470323/ MUSCA_B1_GCC_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470344/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470383/ RSE_TC4_GCC_1_RegBL1_1_Debug_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470411/ RSE_TC4_GCC_2_RegBL1_1_Release_BL2_TFM_BL1_2_IMAGE_BINDING_ENC_OFF_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470414/ MUSCA_B1_GCC_3_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470418/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470420/ MUSCA_B1_GCC_2_RegBL2_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470421/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Debug_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470426/ RSE_TC4_GCC_2_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470427/ MUSCA_B1_GCC_1_Minsizerel_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470430/ MUSCA_B1_ARMCLANG_1_Debug_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470447/ MUSCA_B1_GCC_3_RegBL2_RegS_RegNS_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470448/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470450/ MUSCA_B1_GCC_1_ATTEST_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470456/ MUSCA_B1_GCC_1_FF_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470480/ MUSCA_B1_GCC_3_CRYPTO_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470496/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2_TFM_BL1_2_IMAGE_BINDING_ENC_ON_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470502/ RSE_TC4_GCC_3_RegBL1_1_Release_BL2_CONFIG_TFM_REUSE_COPY_AREA_FOR_SP_STACKS_RSE_XIP_OFF https://ci.trustedfirmware.org/job/tf-m-build-config/470503/ RSE_TC4_GCC_3_RegBL1_1_Debug_BL2_CM_DM_BL2_ECDSA_SIGNING https://ci.trustedfirmware.org/job/tf-m-build-config/470539/ MUSCA_B1_ARMCLANG_1_RegBL2_RegS_RegNS_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470607/ MUSCA_B1_GCC_1_Debug_BL2_MEDIUM-AROT-LESS_PSOFF https://ci.trustedfirmware.org/job/tf-m-build-config/470637/ MUSCA_B1_ARMCLANG_1_CRYPTO_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470683/ RSE_TC4_GCC_1_RegS_RegNS_Debug_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470686/ MUSCA_B1_ARMCLANG_2_STORAGE_Release_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470696/ RSE_TC4_GCC_3_Debug_BL2_CM_DM_BL2_ECDSA_SIGNING https://ci.trustedfirmware.org/job/tf-m-build-config/470704/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS https://ci.trustedfirmware.org/job/tf-m-build-config/470711/ MUSCA_B1_ARMCLANG_3_Release_BL2 https://ci.trustedfirmware.org/job/tf-m-build-config/470716/ MUSCA_B1_ARMCLANG_1_Minsizerel_BL2_MEDIUM-AROT-LESS_MULTI_SIG_SUPPORT https://ci.trustedfirmware.org/job/tf-m-build-config/470719/ RSE_TC4_GCC_3_Release_BL2_RSE_PROVISIONING_SYMMETRIC https://ci.trustedfirmware.org/job/tf-m-build-config/470720/ MUSCA_B1_GCC_3_STORAGE_Minsizerel_BL2_LARGE https://ci.trustedfirmware.org/job/tf-m-build-config/470730/
For detailed build results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/323/artifact/build_results.c... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/324/
Failed Jobs: RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3BBxF9Yr3t3JJF7M... RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3BBxFNHUfkrn2tCi... RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3BBxFWYlmlG9zFYJ...
For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/324/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/321/
Failed Jobs: RSE_TC4_GCC_3_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3B3SIm8DcbpSnc1z...
For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/321/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/320/
Failed Jobs: RSE_TC4_GCC_2_RegS_RegNS_Debug_BL2_ATTESTATION_SCHEME_DPE https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3B0Yz26ThHroL81R...
For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/320/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
Check console output at https://ci.trustedfirmware.org/job/tf-m-nightly/319/
Failed Jobs: RSE_TC4_GCC_1_Debug_BL2 https://tuxapi.tuxsuite.com/v1/groups/tfc/projects/ci/tests/3AxjstzsJYgE30kO...
For detailed test results please refer to https://ci.trustedfirmware.org/job/tf-m-nightly/319/artifact/test_results.cs... IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
tf-m-ci-notifications@lists.trustedfirmware.org
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