TF-M April 2021

tf-m@lists.trustedfirmware.org

17 participants
34 discussions

by Anton Komlev

Hi, The next Technical Forum is planned on Thursday, April 15, 15:00-16:00 UTC (US time zone). Please reply on this email with your proposals for agenda topics. Recording and slides of previous meetings are here: https://www.trustedfirmware.org/meetings/tf-m-technical-forum/ Best regards, Anton

3 years, 5 months

Re: [TF-M] Issues with alignment and buffer locations

by Ken Liu

Hi Jamie, Thanks for your reply. Looks like it is mostly flash related. I have created one task for tracking this: https://developer.trustedfirmware.org/T918 We need some time to analyze this, so the response may be not short and we would keep updating. Feel free to provide your done solutions on the task. Thanks. /Ken From: TF-M <tf-m-bounces(a)lists.trustedfirmware.org> On Behalf Of Jamie Mccrae via TF-M Sent: Thursday, April 1, 2021 4:59 PM To: tf-m(a)lists.trustedfirmware.org Subject: Re: [TF-M] Issues with alignment and buffer locations Hi Ken, > Could help to provide the details so that we can see what the problem is? Looks like you mentioned two problems here, one for the un-aligned memory accessing and another is the FLASH read/write. Sure. This is being based on the nRF5340 (Cortex-M33) chipset, it uses image swapping rather than overwriting, the primary image is located in the on-chip flash and the secondary slot is located in QSPI flash, the scratch slot is also located in QSPI flash, this is the trailing part of the log when the issue with trying to write to QSPI from a non-RAM buffer occurs (GCC build): [ERR] Qerase 0xfe000 [ERR] Qerase 0xff000 [ERR] read area=3, off=0x9fff0, len=0x10 [ERR] Qread 0x9fff0 10 to 0x20005ad8 [ERR] read area=3, off=0x9ffd8, len=0x1 [ERR] Qread 0x9ffd8 1 to 0x20005ad7 [ERR] read area=3, off=0x9ffe0, len=0x1 [ERR] Qread 0x9ffe0 1 to 0x20005b22 [ERR] read area=3, off=0x9ffe8, len=0x1 [ERR] Qread 0x9ffe8 1 to 0x20005b23 [ERR] write area=5, off=0x1ffd8, len=0x4 [ERR] Qwrite 0xfffd8 4 from 0x20005ae0 [ERR] write area=5, off=0x1ffd0, len=0x4 [ERR] Qwrite 0xfffd0 4 from 0x20005ae0 [ERR] write area=5, off=0x1fff0, len=0x10 [ERR] Qwrite 0xffff0 10 from 0xcfdc [ERR] QSPI write failed -400 assertion "rc == 0" failed: file "lib/ext/mcuboot-src/boot/bootutil/src/swap_misc.c", line 125, function: swap_status_init The final write fails because it is attempting to write to QSPI from a non-RAM address, 0xcfdc is an address in the internal flash. Unless this is possibly an issue with the buffer address being overwritten somehow? > For the memory alignment, to ensure the isolation setting all sections should be 32-bytes aligned; and the stack-alignment is 8 bytes. Other contents are set as default, the toolchain should have handled them correctly. This is the error in the trailing part of the log I am getting with it reading 1 byte at a time to an invalid buffer: [ERR] read area=1, off=0, len=0x20 [ERR] Fread 0x10000 0x20 to 0x20002530 [ERR] read area=3, off=0, len=0x20 [ERR] Qread 0x0 0x20 to 0x2000255c [ERR] read area=1, off=0x9fff0, len=0x10 [ERR] Fread 0xafff0 10 to 0x20005b60 [ERR] read area=1, off=0x9ffd8, len=0x1 [ERR] Fread 0xaffd8 1 to 0x20005b5f [ERR] read area=1, off=0x9ffe0, len=0x1 [ERR] Fread 0xaffe0 1 to 0x20005baa [ERR] read area=1, off=0x9ffe8, len=0x1 [ERR] Fread 0xaffe8 1 to 0x20005bab [ERR] read area=5, off=0x1fff0, len=0x10 [ERR] Qread 0xffff0 10 to 0x20005b60 [ERR] read area=5, off=0x1ffd8, len=0x1 [ERR] Qread 0xfffd8 1 to 0x20005b5f [ERR] Qread QSPI failed assertion "rc == 0" failed: file "lib/ext/mcuboot-src/boot/bootutil/src/swap_scratch.c", line 384, function: swap_status_source The 2 issues are QSPI reads must be multiples of 4 bytes, it cannot read just 1 byte, and secondly the 0x20005b5f buffer is not 4-byte aligned so it cannot be used to store the data anyway. The same GCC linker .ld files are being used as are currently in the TF-M repository for the nRF5340-DK which is 4-byte aligned for data and bss and 8-byte aligned for heap. Qread/Qwrite = QSPI, Fread/Write = internal flash, area 5 is the scratch partition. This is TF-M built with separate secure and non-secure image slots. > Please provide the details, thank you! > > /Ken > > From: TF-M <tf-m-bounces at lists.trustedfirmware.org> On Behalf Of Jamie Mccrae via TF-M > Sent: Monday, March 29, 2021 10:19 PM > To: tf-m at lists.trustedfirmware.org > Subject: [TF-M] Issues with alignment and buffer locations > > Hi, > There seems to be a large oversight in the TF-M codeline relating to buffer alignment and locations of buffers, in terms of buffer alignment, some ARM-based silicon has restrictions on buffer alignment, generally 4-byte boundaries, this means that if a non-4 byte boundary address, buffer or data size is provided, the operation cannot be completed. Another issue is that some ARM-based silicon has restrictions on where data can be located, e.g. in RAM only for writing and not from other address spaces. > I am currently trying to get TF-M working on a Nordic nRF53-based designed and have encountered these issues many times, and can see no way to set an alignment, data size or address space limitation in the whole code line which I find to be quite displeasing given that both the silicon and software are ARM-based, I would expect the software you give for silicon based on your reference designs to actually work with it out of the box rather than need lots of work to have these limitations supported. On Nordic silicon, data can only be written and read from RAM e.g. you cannot write to flash from a flash offset, and writes must be 4-byte aligned and 4-byte sized (the QSPI functionality is being used here). > > So I am emailing here to ask: what is the suggestion for dealing with this? Why does the baseline project not (from what I can see) have any sort of support for this? > Thanks, > Jamie THIS MESSAGE, ANY ATTACHMENT(S), AND THE INFORMATION CONTAINED HEREIN MAY BE PROPRIETARY TO LAIRD CONNECTIVITY, INC. AND/OR ANOTHER PARTY, AND MAY FURTHER BE INTENDED TO BE KEPT CONFIDENTIAL. IF YOU ARE NOT THE INTENDED RECIPIENT, PLEASE DELETE THE EMAIL AND ANY ATTACHMENTS, AND IMMEDIATELY NOTIFY THE SENDER BY RETURN EMAIL. THIS MESSAGE AND ITS CONTENTS ARE THE PROPERTY OF LAIRD CONNECTIVITY, INC. AND MAY NOT BE REPRODUCED OR USED WITHOUT THE EXPRESS WRITTEN CONSENT OF LAIRD CONNECTIVITY, INC.

3 years, 6 months

Updated invitation: TF-M Tech forum @ Every 4 weeks from 10am to 11am on Thursday (CDT) (tf-m@lists.trustedfirmware.org)

by Don Harbin

This event has been changed. Title: TF-M Tech forum This is an open forum for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC.Feel free to forward it to colleagues.Details of previous meetings are here: https://www.trustedfirmware.org/meetings/tf-m-technical-forum/==… Info====Trusted Firmware is inviting you to a scheduled Zoom meeting.Topic: TF-M Tech forum - US Time Zone FriendlyTime: Oct 29, 2020 03:00 PM Greenwich Mean Time        Every 4 weeks on Thu, until Mar 18, 2021, 6 occurrence(s)        Oct 29, 2020 03:00 PM        Nov 26, 2020 03:00 PM        Dec 24, 2020 03:00 PM        Jan 21, 2021 03:00 PM        Feb 18, 2021 03:00 PM        Mar 18, 2021 03:00 PMPlease download and import the following iCalendar (.ics) files to your calendar system.Weekly: https://linaro-org.zoom.us/meeting/tJEocOmvpz4tHtYu0Wvn2fOsG91u0kv_ECPd/ics… Zoom Meetinghttps://linaro-org.zoom.us/j/95570795742?pwd=N21YWHJpUjZyS3Fzd0tkOG9hanpidz09Meeting ID: 955 7079 5742Passcode: 177658One tap mobile+12532158782,,95570795742# US (Tacoma)+13462487799,,95570795742# US (Houston)Dial by your location        +1 253 215 8782 US (Tacoma)        +1 346 248 7799 US (Houston)        +1 669 900 9128 US (San Jose)        +1 301 715 8592 US (Germantown)        +1 312 626 6799 US (Chicago)        +1 646 558 8656 US (New York)        877 853 5247 US Toll-free        888 788 0099 US Toll-freeMeeting ID: 955 7079 5742Find your local number: https://linaro-org.zoom.us/u/abx3I7IoRq When: Every 4 weeks from 10am to 11am on Thursday Central Time - Chicago (changed) Where: https://linaro-org.zoom.us/j/95570795742?pwd=N21YWHJpUjZyS3Fzd0tkOG9hanpidz… Calendar: tf-m(a)lists.trustedfirmware.org Who: * Don Harbin - creator * tf-m(a)lists.trustedfirmware.org * anton.komlev(a)arm.com * abdelmalek.omar1(a)gmail.com * kevin.townsend(a)linaro.org * seth(a)nxmlabs.com Event details: https://calendar.google.com/calendar/event?action=VIEW&eid=djczYWZqa3ZmMW5n… Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this courtesy email at the account tf-m(a)lists.trustedfirmware.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively you can sign up for a Google account at https://calendar.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to send a response to the organizer and be added to the guest list, or invite others regardless of their own invitation status, or to modify your RSVP. Learn more at https://support.google.com/calendar/answer/37135#forwarding

3 years, 6 months

Issues with alignment and buffer locations

by Jamie Mccrae

Hi, There seems to be a large oversight in the TF-M codeline relating to buffer alignment and locations of buffers, in terms of buffer alignment, some ARM-based silicon has restrictions on buffer alignment, generally 4-byte boundaries, this means that if a non-4 byte boundary address, buffer or data size is provided, the operation cannot be completed. Another issue is that some ARM-based silicon has restrictions on where data can be located, e.g. in RAM only for writing and not from other address spaces. I am currently trying to get TF-M working on a Nordic nRF53-based designed and have encountered these issues many times, and can see no way to set an alignment, data size or address space limitation in the whole code line which I find to be quite displeasing given that both the silicon and software are ARM-based, I would expect the software you give for silicon based on your reference designs to actually work with it out of the box rather than need lots of work to have these limitations supported. On Nordic silicon, data can only be written and read from RAM e.g. you cannot write to flash from a flash offset, and writes must be 4-byte aligned and 4-byte sized (the QSPI functionality is being used here). So I am emailing here to ask: what is the suggestion for dealing with this? Why does the baseline project not (from what I can see) have any sort of support for this? Thanks, Jamie THIS MESSAGE, ANY ATTACHMENT(S), AND THE INFORMATION CONTAINED HEREIN MAY BE PROPRIETARY TO LAIRD CONNECTIVITY, INC. AND/OR ANOTHER PARTY, AND MAY FURTHER BE INTENDED TO BE KEPT CONFIDENTIAL. IF YOU ARE NOT THE INTENDED RECIPIENT, PLEASE DELETE THE EMAIL AND ANY ATTACHMENTS, AND IMMEDIATELY NOTIFY THE SENDER BY RETURN EMAIL. THIS MESSAGE AND ITS CONTENTS ARE THE PROPERTY OF LAIRD CONNECTIVITY, INC. AND MAY NOT BE REPRODUCED OR USED WITHOUT THE EXPRESS WRITTEN CONSENT OF LAIRD CONNECTIVITY, INC.

3 years, 6 months

2024

2023

2022

2021

2020

2019

2018

TF-M April 2021