It seems that something issue occurs in mailing system.
Anyway, i checked Amjad's answer in "Re: TF-M Digest, Vol 87, Issue 11". Also, i checked M-AXI that can issue 64bit transaction for normal memory in Cortex-M55 TRM.
As you mentioned, the core performs 32bit write-back and actual write to SRAM is performed as 64bit transaction using the cache and M-AXI between the 32bit core and the SRAM.
But, another issue remains
Crypto Cell-312 internal DMA has hardware fixed 32bit data width. It raise partial write event when doing decryption to provisioning data.
Example for this issue can be founded in validate_and_unpack_encrypted_bundle()@bl1_provisioning.c.
To transfer decrypted output to SRAM, it uses internal DMA in CC312.
Should i apply any way to workaround such as no using CC312 DMA or modifying bus width in our situation?
Best Regards RH Kim ----- 원본 메시지 ----- 보낸 사람: 김륜현 <winxp4333@adtek.co.kr> 받는 사람: tf-m@lists.trustedfirmware.org 날짜: 2026-01-09 14:40:45 제목: Handling the SAM partial write
Hi all,
I'm developing the RSE Firmware based on rdv3r1.
I have a concern about the SAM(Security Alarm Manager).
Refering to TRM and codes, for the handling SRAM partial write to sets a correct ECC value,
it read of 64 bits from the captured address(SAM.VMPWCAn) and write the value back to memory at the captured address.
After that, it clears the SAM captured address register and SAM event.
In that scheme, for the 32bit architecture CM55, what correct it everytime seems very overhead and burden if using a SRAM area as data region like stack, heap.
Because 32bit access frequently occurs in 32bit architecture.
Should we avoid using SRAM as data region even though i have found the cases of using SRAM as data region like? Best Regards RH Kim