This event has been updated with a note:
"We have a proposed subject for this TF-A Tech Forum. Joanna"
Changed: description
TF-A Tech Forum
Thursday Sep 22, 2022 ⋅ 4pm – 5pm
United Kingdom Time
Proposed session for this Tech Forum will be an update to Firmware Update
capabilities.More details to follow.....------------------------We run an
open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
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This event has been updated with a note:
"Updated Agenda for 8th September session."
Changed: description
TF-A Tech Forum
Thursday Sep 8, 2022 ⋅ 4pm – 5pm
United Kingdom Time
The plan is to use this Tech Forum session to discuss the LTS proposal and
review comments received.See the TF-A Mailing list for details of the
proposal and review
comments: https://lists.trustedfirmware.org/archives/list/tf-a@lists.t…
will be led by Okash Khawaja and Varun Wadekar.ThanksJoanna
Farley-------------------------------We run an open technical forum call
for anyone to participate and it is not restricted to Trusted Firmware
project members. It will operate under the guidance of the TF
TSC. Feel free to forward this invite to colleagues. Invites are via
the TF-A mailing list and also published on the Trusted Firmware
website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap
mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US
(San Jose)Dial by your location +1 646 558
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Toll-free 888 788 0099 US Toll-freeMeeting ID:
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Hi all,
I want to test how to trap the aborts caused by TZASC.
For example, when I use NS-EL1 (e.g., OS) to access a Secure region
(configured in TZASC), it will generate an abort.
But I am not sure how to trap it. I think it is an external abort, so
I enable the SCR_EL3.EA=1 and write a handler. However I cannot trap
it. Also, my other handlers in EL3 still do not report the abort.
Thus, how can I trap a TZASC abort? If I want to route it into EL3 to
handle, how can I do it?
Sincerely,
WANG Chenxu
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
3 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 3 of 3 defect(s)
** CID 380536: Control flow issues (NO_EFFECT)
/bl32/tsp/tsp_ffa_main.c: 220 in test_memory_send()
________________________________________________________________________________________________________
*** CID 380536: Control flow issues (NO_EFFECT)
/bl32/tsp/tsp_ffa_main.c: 220 in test_memory_send()
214 ERROR("Failed [%u] mmap_add_dynamic_region %u (%lx) (%lx) (%x)!\n",
215 i, ret,
216 (uint64_t)composite->address_range_array[i].address,
217 size, mem_attrs);
218
219 /* Remove mappings created in this transaction. */
>>> CID 380536: Control flow issues (NO_EFFECT)
>>> This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "i >= 0U".
220 for (i--; i >= 0U; i--) {
221 ret = mmap_remove_dynamic_region(
222 (uint64_t)ptr,
223 composite->address_range_array[i].page_count * PAGE_SIZE);
224
225 if (ret != 0) {
** CID 380535: Null pointer dereferences (REVERSE_INULL)
/bl32/tsp/ffa_helpers.c: 154 in memory_retrieve()
________________________________________________________________________________________________________
*** CID 380535: Null pointer dereferences (REVERSE_INULL)
/bl32/tsp/ffa_helpers.c: 154 in memory_retrieve()
148 uint32_t *total_length)
149 {
150 smc_args_t ret;
151 uint32_t descriptor_size;
152 struct ffa_mtd *memory_region = (struct ffa_mtd *)mb->tx_buffer;
153
>>> CID 380535: Null pointer dereferences (REVERSE_INULL)
>>> Null-checking "mb" suggests that it may be null, but it has already been dereferenced on all paths leading to the check.
154 if (retrieved == NULL || mb == NULL) {
155 ERROR("Invalid parameters!\n");
156 return false;
157 }
158
159 /* Clear TX buffer. */
** CID 380534: API usage errors (SWAPPED_ARGUMENTS)
________________________________________________________________________________________________________
*** CID 380534: API usage errors (SWAPPED_ARGUMENTS)
/bl32/tsp/tsp_ffa_main.c: 476 in handle_partition_message()
470
471 default:
472 INFO("TSP Tests: Unknown request ID %d--\n", (int) arg3);
473 }
474
475 /* Swap the sender and receiver in the response. */
>>> CID 380534: API usage errors (SWAPPED_ARGUMENTS)
>>> The positions of arguments in the call to "ffa_msg_send_direct_resp" do not match the ordering of the parameters:
* "receiver" is passed to "sender".
* "sender" is passed to "receiver".
476 return ffa_msg_send_direct_resp(receiver, sender, status, 0, 0, 0, 0);
477 }
478
479 /*******************************************************************************
480 * This function implements the event loop for handling FF-A ABI invocations.
481 ******************************************************************************/
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
This event has been canceled with a note:
"Apologies for the short notice. We have no topic this week and some key
folks are out on vacations. I'm hoping the Techforum on the 8th September
can be a followup LTS discussion on the proposal submitted to the Mailing
list. I'll formally organise that for the 8th next week."
TF-A Tech Forum
Thursday Aug 25, 2022 ⋅ 4pm – 5pm
United Kingdom Time
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap
mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US
(San Jose)Dial by your location +1 646 558
8656 US (New York) +1 669 900
9128 US (San Jose) 877 853 5247 US
Toll-free 888 788 0099 US Toll-freeMeeting ID:
915 970 4974Find your local
number: https://zoom.us/u/ad27hc6t7h
Guests
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okash.khawaja(a)gmail.com
tf-a(a)lists.trustedfirmware.org
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Hi all,
I want to perform some encryption/decryption in TF-A.
I find that Arm provides some hardware-assisted instructions for
encryption and integrity verification (e.g., AESE, SHA1...). But it
seems that FVP does not support them.
I recently read Armv9 and know that Arm purposes SVE/SVE2 to
accelerate the matrix computation. It seems that it can be another
approach to accelerate the encryption.
Since I am a novice in Armv9 (and in FVP), thus, I want to ask:
(1) Do FVP and TF-A support the SVE? If yes, how to configure it?
(2) Do FVP and TF-A support the SVE2? If yes, how to configure it?
Looking forward to your reply!
Sincerely,
WANG Chenxu
Hi,
I am trying to setup and run the RME support in TF-A, using the steps described
here,
https://trustedfirmware-a.readthedocs.io/en/latest/components/realm-managem…
Build goes smoothly and when I launch FVP to run the RME tests using
the command line mentioned in the link, the FVP terminal_0 seems to
be get stuck at the below line,
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.7(debug):v2.7.0-235-g1631f9c75
NOTICE: BL1: Built : 11:44:37, Aug 22 2022
INFO: BL1: RAM 0x4035000 - 0x403c000
INFO: Loading image id=31 at address 0x4001010
INFO: Image id=31 loaded: 0x4001010 - 0x4001258
INFO: FCONF: Config file with image ID:31 loaded at address = 0x4001010
INFO: Loading image id=24 at address 0x4001300
INFO: Image id=24 loaded: 0x4001300 - 0x40015e4
INFO: FCONF: Config file with image ID:24 loaded at address = 0x4001300
INFO: BL1: Loading BL2
INFO: Loading image id=1 at address 0x4022000
INFO: Image id=1 loaded: 0x4022000 - 0x402cca1
NOTICE: BL1: Booting BL2
INFO: Entry point address = 0x4022000
INFO: SPSR = 0x3cd
INFO: Configuring TrustZone Controller
INFO: Total 6 regions set.
Both the tf-a-tests.git and trusted-firmware-a.git are master branch and
I am using the FVP_Base_RevC-2xAEMvA v11.18.16.
I am totally new to this setup and maybe I am missing something here.
Appreciate any help to get this resolved or tips to debug further.
Thanks,
Shameer
Hi Glen, Don, and others,
I've seen that a couple of TF-A patches I've been CCed on recently
often seem to fail the CI run (Allow-CI+1) due to some strange
build-time errors that don't seem to have anything to do with the
patch at hand, and then one of the maintainers usually suggests that
the patch needs a rebase, and the next CI run succeeds after that.
Here are two recent examples:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/16160https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14666
I was wondering if this is a known problem and if the CI can do
anything here to mitigate it and save developers from this extra layer
of friction? I'm not really sure why a rebase was necessary in either
of these examples or why the CI run failed before it (unless the whole
repository was in a bad state that didn't build, but since all
submissions are guarded by the CI that shouldn't have been possible?).
But I also don't really understand why the rebase would make a
difference for the CI anyway. Generally, when a patch is submitted in
Gerrit, that means it is cherry-picked onto the current master
(regardless of what parent commit it was uploaded with). Since the CI
is supposed to be a test run for submission, I would expect that the
CI should also test a patch by cherry-picking it onto the current
master, not just by building the patch on top of whatever parent
commit it was uploaded with. But since rebasing a patch evidently
seems to make a difference to the CI, that suggests that it's
currently doing the latter strategy? Should that maybe be changed to
the former to avoid these kinds of issues?
If this isn't a known problem yet maybe it would be worth adding it to the JIRA?
Thanks,
Julius
Greetings,
Armv9 introduces the RME and GPT technology. The GPT will separates
the memory into unlimited regions with specific attributes. However,
when I read the Armv9 manual and source code of TF-A, I still have
some problems:
1. It seems that GPT is a feature on CPU, but not on a specific device
(e.g.,TZC-400). Thus, will GPT conflict with TZC-400? I mean, when
performing VA->PA on RAM, what is the detailed process if I enable
both GPT and TZC-400?
2. I use the Arm FVP with Armv9 and RME extension enabled, and TF-A is
"arm_cca" branch (with TF-A v2.5). Thus, in this version, what is the
configuration for TZC-400 and GPT? Will it disable TZC-400 (I mean,
GPT only) when booting Normal World?
3. Does GPT handle peripheral access (e.g., from DMA, GPU, Sensors...
etc.)? I know TZC-400 will do it with NSAID.
4. Will GPT configures Read/Write/Execute features?
All comments are valuable!
SIncerely,
WANG Chenxu