This event has been canceled with a note:
"Cancelling this week. I have no topics ready for presenting also many
folks are out on summer holidays. "
TF-A Tech Forum
Thursday Aug 11, 2022 ⋅ 4pm – 5pm
United Kingdom Time
We run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
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All,
This is to inform you all that the TF-A Techforum for Thursday, 19th May 2022 is cancelled as we didn't receive any topic for this week.
The next meeting will now be Thursday, 2nd June 2022 at 16:00 - 17:00 BST.
Thanks,
Bipin Ravi
Hi,
I have tried this before, there is a problem.
on Armv8, when MMU disabled, the default attribute of memory is device,
and device memory access has alignment requirements. For example,
accessing address (0x1) will result in fault.
Ben via TF-A <tf-a(a)lists.trustedfirmware.org> 于2022年7月19日周二 17:02写道:
> Hello,
>
> To decrease feature in BL1, I plan to disable MMU in BL1 stage.
> Are there any potential issues besides performance issues?
>
> BRs
>
> ------------------------------
> Ben(a)tsingmicro.com
> --
> TF-A mailing list -- tf-a(a)lists.trustedfirmware.org
> To unsubscribe send an email to tf-a-leave(a)lists.trustedfirmware.org
>
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
1 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 1 of 1 defect(s)
** CID 379362: Memory - illegal accesses (OVERRUN)
/lib/psci/psci_common.c: 1046 in psci_is_last_on_cpu_safe()
________________________________________________________________________________________________________
*** CID 379362: Memory - illegal accesses (OVERRUN)
/lib/psci/psci_common.c: 1046 in psci_is_last_on_cpu_safe()
1040 unsigned int i = 0;
1041
1042 /*
1043 * Traverse the forest of PSCI nodes, nodes with no parents
1044 * (invalid-nodes) are the root nodes.
1045 */
>>> CID 379362: Memory - illegal accesses (OVERRUN)
>>> Overrunning array "psci_non_cpu_pd_nodes" of 5 16-byte elements at element index 5 (byte offset 95) using index "i" (which evaluates to 5).
1046 while ((psci_non_cpu_pd_nodes[i].parent_node ==
1047 PSCI_PARENT_NODE_INVALID) &&
1048 (i < PSCI_NUM_NON_CPU_PWR_DOMAINS)) {
1049 psci_get_parent_pwr_domain_nodes(
1050 psci_non_cpu_pd_nodes[i].cpu_start_idx,
1051 PLAT_MAX_PWR_LVL, parent_nodes);
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
Hello,
To decrease feature in BL1, I plan to disable MMU in BL1 stage.
Are there any potential issues besides performance issues?
BRs
Ben(a)tsingmicro.com
Hi All,
Is there any public BL31 memory usage data, such as static image size
and runtime memory usage, with different feature enabled?
For example,
typical PSCI feature would require image size XXKB, runtime memory XXKB.
enabling FFA would enlarge image size by XXKB, runtime memory enlarge XXKB.
we are evaluating how much On-Chip RAM could be assigned for BL31,
if there are any public data available, that would be great.
Thanks,
Peng.
Hi,
There have been discussions about having long term support releases
for TF-A, e.g. the email thread [1] and a tech forum [2]. For partners
releasing TF-A in their production devices, LTS is very much needed.
From the previous discussions, it seems like there is an agreement
that LTS is a good idea but we need to build consensus on how to
support it. Any thoughts on this?
Thanks,
Okash
[1] https://lists.trustedfirmware.org/archives/search?mlist=tf-a%40lists.truste…
[2] https://www.trustedfirmware.org/docs/TF-A-LTS.pdf
Hi all,
I am using FVP base RevC. Recently I heard that this FVP supports a
Mali G76 GPU, and I want to test it.
To configure it, initially I add a node in
linux/arch/arm64/boot/dts/arm/fvp-base-aemv8a-aemv8a.dtsi, but it
doesn't work. Finally, I find that I should configure
trusted-firmware-a/fdts/fvp-base-gicv3-psci-1t.dts, and I can see a
mali GPU node in /proc/device-tree.
One of my booting command (sorry, the entire booting command is TOO
long) is "--data
cluster0.cpu0=arm-reference-platform/output/fvp/fvp-oe/uboot/fvp-base-aemv8a-aemv8a.dtb@0x82000000".
And I use the following shell command to compile the TF-A: make
PLAT=fvp all CROSS_COMPILE=aarch64-none-elf- ENABLE_RME=1 DEBUG=1
ARCH=aarch64 fip
BL33=arm-reference-platform/output/fvp/components/fvp/uboot.bin
FVP_HW_CONFIG_DTS=fdts/fvp-base-gicv3-psci-1t.dts
ARM_DISABLE_TRUSTED_WDOG=1.
So, I wonder, why the real DTS is in TF-A, instead of Linux?
BTW, I wanna ask another question (although it is not proper to ask
here, I cannot find FVP's mailing list): Can someone provide a proper
dts configurations for FVP's Mali G76 GPU?
Sincerely,
WANG Chenxu
This event has been updated with a note:
"Updated Agenda for 14th July TF-A TechForum session next week."
Changed: description
TF-A Tech Forum
Thursday Jul 14, 2022 ⋅ 4pm – 5pm
United Kingdom Time
AgendaLTS (Long Term Support) Releases DiscussionLed by Okash Khawaja
(Google) and Varun Wadekar (NVIDIA)An initial discussion on some of
the requirements and open questions of providing TF-A LTS releases. This
initial session will concentrate on the technical aspects of LTS releases
with suggestions and examples. Latter sessions can be expected to bring
into the discussion resourcing and funding considerations.The hope is to
establish and exchange views of the project community interest on this
topic.==============================================================================We
run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap
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9128 US (San Jose) 877 853 5247 US
Toll-free 888 788 0099 US Toll-freeMeeting ID:
915 970 4974Find your local
number: https://zoom.us/u/ad27hc6t7h
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