TF-A Community,
This is to notify that we are planning to target the Trusted Firmware-A 2.7 release during the fourth week of May 2021 as part of the regular 6 month cadence. This is a little later than originally targeted due to the number of patches still under review from contributors.
The aim is to consolidate all TF-A work since the 2.6 release. As part of this, a release candidate tag will be created and release activities will commence some time during the week ending 20th May 2022 across all TF-A repositories.
Any major enhancement patches still open after that date will not be merged until after the release.
This release will involve the various repositories making up the broader TF-A project including the TF-A mainline, TF-A Tests, Hafnium, TF-A CI Scripts and TF-A CI Jobs.
We will endeavour minimise the disruption on patch merging and complete release activities ASAP after we start.
Thanks
Joanna
This event has been changed.
Title: TF-A Tech Forum
Topic: Feature Detection MechanismPresented by : Jayanth
ChidanandAgenda:Feature detection mechanism is a diagnostic tool to quickly
check and get assured of whether the architectural features enabled by
software match with the given hardware implementation at an early stage of
booting. It aims at mitigating the runtime-exceptions.I will be covering
the implementation work completed so far and the impact ofReferences:TF-A
Mailing List
PostPatchesDocumentation=================================================We
run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
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This event has been changed.
Title: TF-A Tech Forum
Topic: Feature Detection MechanismPresented by : Jayanth
ChidanandAgenda:Feature detection mechanism is a diagnostic tool to quickly
check and get assured of whether the architectural features enabled by
software match with the given hardware implementation at an early stage of
booting. It aims at mitigating the runtime-exceptions.I will be covering
the implementation work completed so far and the impact ofReferences:TF-A
Mailing List
PostPatchesDocumentation=================================================We
run an open technical forum call for anyone to participate and it is not
restricted to Trusted Firmware project members. It will operate under the
guidance of the TF TSC. Feel free to forward this invite to
colleagues. Invites are via the TF-A mailing list and also published on the
Trusted Firmware website. Details are
here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr…
Firmware is inviting you to a scheduled Zoom meeting.Join Zoom
Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap
mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US
(San Jose)Dial by your location +1 646 558
8656 US (New York) +1 669 900
9128 US (San Jose) 877 853 5247 US
Toll-free 888 788 0099 US Toll-freeMeeting ID:
915 970 4974Find your local
number: https://zoom.us/u/ad27hc6t7h (changed)
When: Thu Apr 21, 2022 4pm – 5pm United Kingdom Time
Calendar: tf-a(a)lists.trustedfirmware.org
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* Bill Fletcher - creator
* marek.bykowski(a)gmail.com
* okash.khawaja(a)gmail.com
* tf-a(a)lists.trustedfirmware.org
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Hi,
I've started to experiment with MTE in OP-TEE at S-EL1. I've compiled
TF-A with CTX_INCLUDE_MTE_REGS and I'm testing this on QEMU. Before
trying to use MTE in OP-TEE I check id_aa64pfr1_el1 and skip MTE
initializations if unavailable.
This works as long as TF-A always is compiled with
CTX_INCLUDE_MTE_REGS if MTE is available. If TF-A is compiled without
CTX_INCLUDE_MTE_REGS OP-TEE will be trapped into EL3 when trying to
access one of the MTE registers. I suppose this is because SCR_EL3.ATA
is 0. Is there a way for OP-TEE to tell if the MTE registers are safe
to access?
Thanks,
Jens
Hi,
I'm working on a hobby project: AARCH64 Hypervisor on Raspberry Pi 4b. I
have a problem with trapping a psci smc. I'll explain everything and what
steps I have followed.
Right now, I'm implementing SMC trapping. I can successfully forward almost
all SMCs except for PSCI_CPU_ON_AARCH64. Linux makes these SMCs to bring
up secondary CPUs during booting. Here's what I'm trying to do:
- trap the PSCI_CPU_ON_AARCH64 SMC,
- preserve the entry_point address in global variable
- replace the entrypoint with my entrypoint and make the smc to tf-a(or
simply forward it.)
- when secondary cpus come online at the given address, where I set
their stack point and then eret the original address.
Secondary cpus won't come online at the given address. Even if I don't
change any arguments of CPU_ON smc and forward it as it is, the secondary
cpus still won't come online. However, without trapping
enabled(HCR_EL2.TSC=0), everything works fine.
I tried to debug inside Trusted Firmware. I know that overall path for
secondary CPU hotplug in is:
CPU released from reset -> (ROM and possibly some other bootloader) ->
bl31/aarch64/bl31_entrypoint.S:bl31_warm_entrypoint() ->
lib/psci/psci_common.c:psci_warmboot_entrypoint() ->
lib/psci/psci_on.c:psci_cpu_on_finish() -> rpi3_pwr_domain_on_finish()
I printed at all these points in Trusted Firmware with and without trapping
enabled. Here's what I found: Nothing gets printed anywhere in that path if
trapping is enabled. However, without trapping enabled, I can print
anywhere even in bl31_entrypoint.S:bl31_warm_entrypoint(). What could be
the problem?
Here's my code:
https://github.com/SikkiLadho/Leo/blob/4f272eff39934058a7f989c91aad82eab810…
--
Mushahid Hussain
Hello,
Are there any immediate plans to add support for Cortex-X1 in TF-A? If
not then I'll be happy to submit CL for it. For start, it will cover a
subset of errata workarounds. Then people can add more as needed. Let
me know what you think.
Thanks,
Okash