- TF-A - lists.trustedfirmware.org

MISRA-C violation for Device Tree (FDT) in Trusted Firmware-A (TFA) code.

by Nithin G

Hello, It is observed that device tree functions are present under lib/libfdt/... in Trusted Firmware-A code, but this device tree are not present in symbol table and also if we remove this device tree functions in code, board was successfully booting. However, while doing Coverity build to fix MISRA-C violations getting violations from this device tree code. So, is it possible to leave those violations please suggest? And when it will be enabled, please suggest. Thanks & Regards Nithin G

2 years, 8 months

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Techforum for 24th August CANCELLED

by Joanna Farley

Hi Everyone, I have cancelled the TF-A techforum for latter today as we have no topic scheduled to be discussed. Calendar cancellations have been sent. Apologies for the late notification. Joanna

2 years, 9 months

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Canceled event with note: TF-A Tech Forum @ Thu Aug 24, 2023 4pm - 5pm (BST) (tf-a@lists.trustedfirmware.org)

by joanna.farley＠arm.com

This event has been canceled with a note: "Cancelling as we have no topics for today. Apologies for the late cancellation. Joanna" TF-A Tech Forum Thursday Aug 24, 2023 ⋅ 4pm – 5pm United Kingdom Time We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr… Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location        +1 646 558 8656 US (New York)        +1 669 900 9128 US (San Jose)        877 853 5247 US Toll-free        888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h   Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

2 years, 9 months

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Question about Secondary CPU boot with spintable

by 빈성욱

Hi I ported TF-A and OPTEE on multi-core SoC, and I checked that xtest passed on CPU0 without failure. However, I'm failing in secondary CPU boot, and I'd like to get some help. I'm using ARMv8, and I'm using spintable as CPU enable method (not using PSCI FW). TF-A is in EL3. What I did ... 1. I released secondary CPU reset from bl31_early_platform_setup2() during primary CPU cold booting - set secondary CPU's RVBAR to bl31_entrypoint - release secondary CPU reset 2. I implemeneted plat_secondary_cold_boot_setup(), which is spining until linux kernel updates cpu-release-addr. Once linux kernel updates cpu-release-addr, then it changes EL to EL1 and jumps to secondary_startup() in linux 3. But secondary core goes to panic. It seems to happen when linux invokes optee_probe() Should I initialize some contexts (e.g. optee ..)? If so, where should I implement the corresponding codes? I'm wondering if I'm missing something, and I'd like to get some advice Thanks, --Bin

2 years, 9 months

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Canceled event with note: TF-A Tech Forum @ Thu Aug 10, 2023 4pm - 5pm (BST) (tf-a@lists.trustedfirmware.org)

by joanna.farley＠arm.com

This event has been canceled with a note: "Cancelling this weeks TF-A Tech Forum. No topics ready to present and many people out on vacation." TF-A Tech Forum Thursday Aug 10, 2023 ⋅ 4pm – 5pm United Kingdom Time We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: https://www.trustedfirmware.org/meetings/tf-a-technical-forum/Tr… Firmware is inviting you to a scheduled Zoom meeting.Join Zoom Meetinghttps://zoom.us/j/9159704974Meeting ID: 915 970 4974One tap mobile+16465588656,,9159704974# US (New York)+16699009128,,9159704974# US (San Jose)Dial by your location        +1 646 558 8656 US (New York)        +1 669 900 9128 US (San Jose)        877 853 5247 US Toll-free        888 788 0099 US Toll-freeMeeting ID: 915 970 4974Find your local number: https://zoom.us/u/ad27hc6t7h   Guests marek.bykowski(a)gmail.com okash.khawaja(a)gmail.com tf-a(a)lists.trustedfirmware.org ~~//~~ Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this email because you are an attendee on the event. To stop receiving future updates for this event, decline this event. Forwarding this invitation could allow any recipient to send a response to the organizer, be added to the guest list, invite others regardless of their own invitation status, or modify your RSVP. Learn more https://support.google.com/calendar/answer/37135#forwarding

2 years, 9 months

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Trusted Firmware-A LTS v2.8.8 Release Announcement

by Varun Wadekar

Hello, Trusted Firmware-A LTS version 2.8.8 is now available. This release contains the following patches. * ec3fafa24 fix(cpus): workaround for Neoverse V2 erratum 2801372 The readthedocs update can be found at https://trustedfirmware-a.readthedocs.io/en/lts-v2.8/change-log.html. Thanks.

2 years, 9 months

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About erratum in TF-A

by Ming Huang

Hi Boyan, Some questions about erratum in TF-A: 1 Why workaround's flag is 0? In my mind, all flag should be 1 because there is func to check cpu revisions, such as check_errata_2326639. 43438ad1a patch: +ERRATA_N2_2326639 ?=0 2 After e444763d6(shorten errata flag defines) patch, introduce CPU_FLAG_LIST, Is the workaround's flag change to 1? e444763d6 patch: -ERRATA_N2_2326639 ?=0 +CPU_FLAG_LIST += ERRATA_N2_2326639 Regards, Ming

2 years, 9 months

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New Defects reported by Coverity Scan for ARM-software/arm-trusted-firmware

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 397932: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /lib/extensions/amu/aarch64/amu.c: 212 in amu_init_el3() ________________________________________________________________________________________________________ *** CID 397932: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /lib/extensions/amu/aarch64/amu.c: 212 in amu_init_el3() 206 } 207 } 208 209 void amu_init_el3(void) 210 { 211 uint64_t group0_impl_ctr = read_amcgcr_el0_cg0nc(); >>> CID 397932: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "1 << group0_impl_ctr" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). 212 uint64_t group0_en_mask = (1 << (group0_impl_ctr)) - 1U; 213 uint64_t num_ctr_groups = read_amcfgr_el0_ncg(); 214 215 /* Enable all architected counters by default */ 216 write_amcntenset0_el0_px(group0_en_mask); 217 ** CID 397931: (DEADCODE) /plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c: 153 in bl31_early_platform_setup2() /plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c: 150 in bl31_early_platform_setup2() /plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c: 146 in bl31_early_platform_setup2() ________________________________________________________________________________________________________ *** CID 397931: (DEADCODE) /plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c: 153 in bl31_early_platform_setup2() 147 imx_csu_init(csu_cfg); 148 149 #if IMX_BOOT_UART_BASE 150 console_base = IMX_BOOT_UART_BASE; 151 #endif 152 if (console_base == 0U) { >>> CID 397931: (DEADCODE) >>> Execution cannot reach this statement: "console_base = imx8m_uart_g...". 153 console_base = imx8m_uart_get_base(); 154 } 155 156 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 157 IMX_CONSOLE_BAUDRATE, &console); 158 /* This console is only used for boot stage */ /plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c: 150 in bl31_early_platform_setup2() 144 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 145 146 #if IMX_BOOT_UART_BASE 147 console_base = IMX_BOOT_UART_BASE; 148 #endif 149 if (console_base == 0U) { >>> CID 397931: (DEADCODE) >>> Execution cannot reach this statement: "console_base = imx8m_uart_g...". 150 console_base = imx8m_uart_get_base(); 151 } 152 153 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 154 IMX_CONSOLE_BAUDRATE, &console); 155 /* This console is only used for boot stage */ /plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c: 146 in bl31_early_platform_setup2() 140 mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000); 141 142 #if IMX_BOOT_UART_BASE 143 console_base = IMX_BOOT_UART_BASE; 144 #endif 145 if (console_base == 0U) { >>> CID 397931: (DEADCODE) >>> Execution cannot reach this statement: "console_base = imx8m_uart_g...". 146 console_base = imx8m_uart_get_base(); 147 } 148 149 console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, 150 IMX_CONSOLE_BAUDRATE, &console); 151 /* This console is only used for boot stage */ ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

2 years, 10 months

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FYI: Session on OpenCI and MISRA

by Don Harbin

Hi All, I wanted to let you know that next Thursday, July 27th, the TF-A Tech Forum will be hosting a presentation on OpenCI and MISRA presented by Paul Sokolovski of Linaro and Roberto Bagnara from Bugseng. MISRA is being enabled on both TF-A and TF-M in OpenCI, so sending this out to both lists since users in both domains may be interested in the session. Meeting time and dial up info can be found in the TF community calendar located here: https://www.trustedfirmware.org/meetings/ Best Regards, Don Harbin TrustedFirmware Community Manager don.harbin(a)linaro.org

2 years, 10 months

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The increasing size of BL31

by Okash Khawaja

Hi, Typically, BL31 runs in SRAM which tends to be limited. As we add support for newer architectural features e.g. CCA, general features and standards, the size of BL31 image will grow and become harder to fit in most SRAMs. This email is to share ideas on how to address this problem. A simple approach will be to identify parts of NOBITS ELF sections of BL31 which can be moved out to DRAM. Since NOBITS sections aren't part of the file image, loading and authentication code doesn't have to change. The challenge will be to come up with some criteria to help decide what kind of buffers can be kept in DRAM vs SRAM. Other ideas are also welcome. Please share your thoughts. Thanks, Okash

2 years, 10 months

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