Hello,
I am working on a board based on NXP LS1043 processor (arm64) with TPM2 on SPI interface.
I have the following boot sequence : TF-A + UBOOT + YOCTO.
I have a look on the code where the TF-A MEASURE_BOOT was implemented for the fvp arm platform using OPTEE fTPM.
As far as I understood, the event log is implemented based on the TCG2 EFI PROTOCOL from commit :
commit 3ee148d6439b69d326f8e6d2a4ce822604e0e64c
Merge: 43f7d8879 4a135bc33
Author: joanna.farley <joanna.farley(a)arm.com>
Date: Wed Jul 22 16:35:11 2020 +0000
Nevertheless, I am surprised because I did not find any TPM2 driver in the current TF-A code.
I would like to know :
1. How to port what was done for the fvp platform to my platform ?
2. What is code hashed in the TFA to create the event log ?
3. Why are there no TPM2 routine in the TF-A to expend PCR ?
Thanks in advance for your help
Benoit
Hi,
The PSCI specification defines two different power state coordination modes
for CPU_SUSPEND that can be used to put a core or a group of cores into a
low-power state. These modes are the platform-coordinated mode (default)
and the OS-initiated mode (optional). OS-initiated mode is currently not
supported by TF-A, while both modes are supported by the Linux Kernel.
Requesting reviews for the patches [1] adding support for OS-initiated mode
in TF-A and the corresponding tests in TF-A-Tests. Any feedback and
comments are much appreciated.
Thanks in advance!
Wing
[1] https://review.trustedfirmware.org/q/topic:psci-osi
Hello,
I'm a noob here, and I need help. I've just built flash-image.bin for
my MACCHIATObin Single Shot as follows, but it fails to boot - as
follows further below:
- git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
- Clone the binaries-marvell and mv-ddr-marvell Git repos alongside the
trusted-firmware-a, and check out revisions as recommeded in TF-A build
instructions for Armada80x0
(https://trustedfirmware-a.readthedocs.io/en/latest/plat/marvell/armada/buil…).
- export
CROSS_COMPILE=/my/path/to/arm-gnu-toolchain/11.3.rel1-x86_64-aarch64-none-elf/bin/aarch64-none-elf-
- Build u-boot.bin:
- git clone https://source.denx.de/u-boot/u-boot.git alongside the
binaries-marvell and mv-ddr-marvell repos.
- cd u-boot
- git checkout v2023.01 - the latest release.
- make mvebu_mcbin-88f8040_defconfig
- Change CONFIG_DEFAULT_DEVICE_TREE to "armada-8040-mcbin-singleshot"
(inspired by this SolidRun doc:
https://github.com/SolidRun/documentation/blob/bsp/8040/u-boot.md).
- Add arch/arm/dts/armada-8040-mcbin-singleshot.dts. Can be obtained
e.g. from the latest Marvell kernel sources
(https://github.com/torvalds/linux/blob/master/arch/arm64/boot/dts/marvell/).
- make
- Built fine.
- Build TF-A:
- cd ../trusted-firmware-a/
- git checkout v2.8.0 - the latest release, as per changelog
(https://trustedfirmware-a.readthedocs.io/en/latest/change-log.html).
- make PLAT=a80x0_mcbin MV_DDR_PATH=../mv-ddr-marvell
SCP_BL2=../binaries-marvell/mrvl_scp_bl2.img BL33=../u-boot/u-boot.bin
mrvl_flash
- Built fine.
Then I flashed the flash-image.bin onto my SD card: dd
if=trusted-firmware-a/build/a80x0_mcbin/release/flash-image.bin
of=/dev/mmcblk0 seek=4096 conv=fdatasync,notrunc (as per
https://archlinuxarm.org/platforms/armv8/marvell/macchiatobin).
It boots, but complains about a missing serial driver and resets in a loop:
---
BootROM - 2.03
Starting CP-0 IOROM 1.07
Booting from SD 0 (0x29)
Found valid image at boot postion 0x002
lNOTICE: Starting binary extension
NOTICE: SVC: DEV ID: 8040, FREQ Mode: 0xd
NOTICE: SVC: AVS work point changed from 0x29 to 0x29
mv_ddr: devel-g541616b (Mar 05 2023 - 14:15:32)
mv_ddr: completed successfully
NOTICE: Cold boot
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.8(release):v2.8
NOTICE: BL1: Built : 14:15:45, Mar 5 2023
NOTICE: BL1: Booting BL2
NOTICE: BL2: v2.8(release):v2.8
NOTICE: BL2: Built : 14:15:48, Mar 5 2023
NOTICE: SCP_BL2 contains 7 concatenated images
NOTICE: Load image to CP1 MG
NOTICE: Loading MG image from address 0x402305c Size 0xe0f0 to MG at
0xf4100000
NOTICE: Load image to CP0 MG
NOTICE: Loading MG image from address 0x403114c Size 0xe0f0 to MG at
0xf2100000
NOTICE: Skipping MSS CP3 related image
NOTICE: Skipping MSS CP2 related image
NOTICE: Load image to CP1 MSS AP0
NOTICE: SECURELY Loading MSS FW from addr. 0x4042c34 Size 0x1cfc to MSS
at 0xf4280000
NOTICE: CP MSS startup is postponed
NOTICE: Done
NOTICE: Load image to CP0 MSS AP0
NOTICE: SECURELY Loading MSS FW from addr. 0x4044930 Size 0x1cfc to MSS
at 0xf2280000
NOTICE: CP MSS startup is postponed
NOTICE: Done
NOTICE: Load image to AP0 MSS
NOTICE: Loading MSS FW from addr. 0x404662c Size 0x5400 to MSS at
0xf0580000
NOTICE: Done
NOTICE: SCP Image doesn't contain PM firmware
NOTICE: BL1: Booting BL31
lNOTICE: Starting CP0 MSS CPU
NOTICE: Starting CP1 MSS CPU
NOTICE: MSS PM is not supported in this build
NOTICE: BL31: v2.8(release):v2.8
NOTICE: BL31: Built : 14:15:55, Mar 5 2023
<debug_uart>
No serial driver found
resetting ...
---
Can anyone advise how to fix this? Is this list even the right place to
ask such questions?
Maciej
--
Maciej Sieczka
http://www.sieczka.org
Hi,
Please find the latest report on new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
2 new defect(s) introduced to ARM-software/arm-trusted-firmware found with Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 383288: (CHECKED_RETURN)
/mbedtls/library/bignum.c: 1670 in mbedtls_mpi_exp_mod()
/mbedtls/library/bignum.c: 1867 in mbedtls_mpi_exp_mod()
________________________________________________________________________________________________________
*** CID 383288: (CHECKED_RETURN)
/mbedtls/library/bignum.c: 1670 in mbedtls_mpi_exp_mod()
1664 *
1665 * To achieve this, we make a copy of X and we use the table entry in each
1666 * calculation from this point on.
1667 */
1668 const size_t x_index = 0;
1669 mbedtls_mpi_init( &W[x_index] );
>>> CID 383288: (CHECKED_RETURN)
>>> Calling "mbedtls_mpi_copy" without checking return value (as is done elsewhere 43 out of 46 times).
1670 mbedtls_mpi_copy( &W[x_index], X );
1671
1672 j = N->n + 1;
1673 /* All W[i] and X must have at least N->n limbs for the mpi_montmul()
1674 * and mpi_montred() calls later. Here we ensure that W[1] and X are
1675 * large enough, and later we'll grow other W[i] to the same length.
/mbedtls/library/bignum.c: 1867 in mbedtls_mpi_exp_mod()
1861 MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &W[x_index], N, &W[x_index] ) );
1862 }
1863
1864 /*
1865 * Load the result in the output variable.
1866 */
>>> CID 383288: (CHECKED_RETURN)
>>> Calling "mbedtls_mpi_copy" without checking return value (as is done elsewhere 43 out of 46 times).
1867 mbedtls_mpi_copy( X, &W[x_index] );
1868
1869 cleanup:
1870
1871 /* The first bit of the sliding window is always 1 and therefore the first
1872 * half of the table was unused. */
** CID 383287: Null pointer dereferences (FORWARD_NULL)
________________________________________________________________________________________________________
*** CID 383287: Null pointer dereferences (FORWARD_NULL)
/mbedtls/library/rsa_alt_helpers.c: 134 in mbedtls_rsa_deduce_primes()
128
129 for( ; attempt < num_primes; ++attempt )
130 {
131 mbedtls_mpi_lset( &K, primes[attempt] );
132
133 /* Check if gcd(K,N) = 1 */
>>> CID 383287: Null pointer dereferences (FORWARD_NULL)
>>> Passing "P" to "mbedtls_mpi_gcd", which dereferences null "P->p".
134 MBEDTLS_MPI_CHK( mbedtls_mpi_gcd( P, &K, N ) );
135 if( mbedtls_mpi_cmp_int( P, 1 ) != 0 )
136 continue;
137
138 /* Go through K^T + 1, K^(2T) + 1, K^(4T) + 1, ...
139 * and check whether they have nontrivial GCD with N. */
________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…
mmc_enumerate() is the only caller of mmc_send_op_cond().
mmc_enumerate() calls mmc_reset_to_idle() just before calling
mmc_send_op_cond(). No need to do that again in mmc_send_op_cond().
Signed-off-by: Baruch Siach <baruch(a)tkos.co.il>
Change-Id: Ib8c8ed1a559e3fecb315245f91bb3dc1f547d820
---
Sending the patch to the list once again. review.trustedfirmware.org
does not work for me.
https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.…
---
drivers/mmc/mmc.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 2b727d4e7696..57f47482013a 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -452,11 +452,6 @@ static int mmc_send_op_cond(void)
int ret, n;
unsigned int resp_data[4];
- ret = mmc_reset_to_idle();
- if (ret != 0) {
- return ret;
- }
-
for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
ret = mmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
--
2.39.2
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Hi,
In ARM TBBR, there is a requirement
“R0100_TBBR_AFM_FLASHING” (The AP firmware must switch to the Non-Trusted world for executing the SoC firmware loader),
But there is no requirement for secure boot as long as I finish chain if ROT verification.
So, can I implement FWU in BL2 which is verified and load from BL1 (ROM)?
For example,
BL1(ROM) -> Load and verify BL2U with new image from SD to secure RAM -> execute BL2U in Secure RAM then write new image to NAND flash
Best regards,
Jun
This event has been updated
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architecture.A more detailed agenda will be issued closer to the
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Agenda UpdateTitle:PSCI OS-initiated mode in TF-APresented by:Maulik Shah,
Ulf Hansson, Wing LiAgenda:1. Overview of OS-initiated mode2. Why
OS-initiated mode?3. Implementation details and testing in TF-AThanks
AllJoanna===============================We run an open technical forum call
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